1. Field of the Invention
This disclosure relates to random access memory and specifically to a serial address generator for a burst-type random access memory.
2. Description of the Prior Art
Video RAM (random access memory), synchronous RAM and burst RAM each require a sequence of internally generated addresses for faster cycling and prevention of the external address bus lines from fast switching to suppress switching noise in the system. Typically the start address of a particular address burst is provided from an external source (a host computer or a processor) and as subsequent clock signals arrive at the address generator, the following addresses in the burst are generated continuously in sequence for the duration of the burst. The prior art presets the address sequencer (typically a counter) to the externally provided start address (A.sub.n) in response to a PRESET signal. The address sequencer output is updated with each .phi..sub.clock rising edge, and the outputs of the address generator are sequentially A.sub.n, A.sub.n+1, A.sub.n+2, etc.
Such a prior art address generator is shown in FIG. 1A including address sequencer 12 outputting the sequence of addresses to an output buffer 14. The three input signals to the address sequencer 12 are the input address signal (the start address A.sub.n), the .phi..sub.clock signal, and the PRESET signal. Additionally, a sequence control signal controls whether the address sequencer 12 counts up or down. In most applications, upcounting is used, and this function is built in, rather than being a control function. The associated timing diagram is shown in FIG. 2A.
Typically the address sequencer 12 (counter) includes a master side and a slave side, each initially set to the start address A.sub.n. It is to be understood that the device of FIG. 1A is a parallel device, where the start address A.sub.n is a multi-bit address provided by a plurality of lines, i.e. an address bus. The address out signal is also provided on a multi-line bus.
As seen in FIG. 2A, the first address out A.sub.n is output to buffer 14 when the Preset signal is applied, and kept until leading edge of .phi..sub.clock arrives. The second address out A.sub.n+1 is output to buffer 14 at the trailing edge of .phi..sub.clock and the following addresses are updated at every trailing edge of the .phi..sub.clock signal.
The address generator of FIG. 1A functions adequately; however it is slower than desired. Faster operation is desirable to improve system performance such as needed in a typical burst DRAM (dynamic random access memory) chip. The FIG. 1A address generator delivers the first address late, due to the propagation delay through the counters inside the address sequencer. This means a shorter start address duration time.
To improve the start address delivery, in a second prior art address generator the start address is provided from the Address Input directly, instead of going through the counters. (See FIG. 1B, and corresponding timing diagram FIG. 2B).
Rather than providing the start address A.sub.n to the address sequencer as in FIG. 1A, the address sequencer 12 of FIG. 1B is bypassed before and during the preset period by means of external address enable switch 24 and internal address enable switch 26, and the start address is provided directly to the output buffer via external address enable switch 24. This (start) address A.sub.n is therefore available almost immediately as the address out at buffer 14, without processing by the address sequencer 12.
However, further performance improvement (i.e., higher speed) is desirable in terms of address output.